(a) Field of the Invention
The present invention relates to a method of forming an electrode pattern on a surface of a GaAs semiconductor substrate and a novel electrode pattern formed of a metal multilayer obtained thereby.
Note that in this specification, an electrode pattern includes an electrode wiring layer, a bonding pad and similar conductive layers.
(b) Description of the Prior Art
A GaAs FET electrode wiring layer or bonding pad having a three-layered structure of Au/Pt/Ti (elements described on the left hereinafter denote uppermost layers unless otherwise noted) or a two-layered structure of Al/Ti is conventionally known. The electrode wiring layer or the bonding pad is sometimes formed by a wet etching method but mainly by a lift-off method.
A method of forming a bonding pad by wet etching will be described hereinafter. In this case, an insulating film is formed on a GaAs semiconductor substrate by CVD, and thereafter a contact hole is selectively formed in the insulating film. A metal film for forming a bonding pad is deposited on the overall surface of the substrate, and a resist pattern is formed thereon. Finally, the metal film is etched by wet etching using the resist pattern as a mask so as to form a bonding pad of the metal film on the hole of the insulating film. In this method, since the GaAs semiconductor layer is highly sensitive to chemical treatment, when the wet etching method is used, side etching occurs. For this reason, this method is unappropriate for forming a micropattern such as a gate electrode. Note that in a GaAs FET, a submicron micropattern must be formed.
Therefore, a lift-off method has been developed for micropatterning. This method is described in U.S. Pat. No. No. 3,994,758. However, the metal film formed by this method is formed by CVD at a low temperature because of a resist film. For this reason, bonding between a metal multilayer and a semiconductor substrate constituting an electrode pattern is inadequate. Therefore, the electrode pattern is easily removed during lifting off or wire bonding, thus degrading the yield in manufacturing of the GaAs FET.